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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . d u a l - p h a s e s y n c h r o n o u s - r e c t i f i e r b u c k c o n t r o l l e r f e a t u r e s g e n e r a l d e s c r i p t i o n v o l t a g e - m o d e o p e r a t i o n w i t h c u r r e n t s h a r i n g o p e r a t e w i t h 4 . 5 v ~ 1 3 . 2 v s u p p l y v o l t a g e support single and two-phase operations + 2% reference voltage accuracy over temperature l o s s - l e s s i n d u c t o r d c r c u r r e n t s e n s i n g a d j u s t a b l e o v e r c u r r e n t p r o t e c t i o n u s e d c r c u r r e n t s e n s i n g programmable pwm switching frequency from 100khz to 800khz d y n a m i c o u t p u t v o l t a g e a d j u s t m e n t a d j u s t a b l e s o f t - s t a r t q f n 4 x 4 - 2 4 p a c k a g e h a l o g e n a n d l e a d f r e e a v a i l a b l e ( r o h s c o m p l i a n t ) a p p l i c a t i o n s v g a m o t h e r b o a r d t h e a p w 8 7 0 0 , t w o - p h a s e p w m c o n t r o l i c , p r o v i d e s a p r e c i s i o n v o l t a g e r e g u l a t i o n s y s t e m f o r a d v a n c e d g r a p h i c c a r d a n d m o t h e r b o a r d a p p l i c a t i o n s . t h e i n t e g r a t i o n o f p o w e r m o s f e t d r i v e r s i n t o t h e c o n t r o l l e r i c a n d r e d u c e s t h e n u m b e r o f e x t e r n a l p a r t s f o r a c o s t a n d s p a c e s a v i n g p o w e r m a n a g e m e n t s o l u t i o n . t h e a p w 8 7 0 0 u s e s a v o l t a g e - m o d e p w m a r c h i t e c t u r e , o p e r a t i n g w i t h a d j u s t f r e q u e n c y f r o m 1 0 0 k h z t o 8 0 0 k h z . t h e d e v i c e u s e s t h e v o l t a g e a c r o s s t h e d c r s o f t h e i n - d u c t o r s f o r c u r r e n t s e n s i n g a c h i e v e s h i g h e f f i c i e n c y . t h e d e v i c e i n t e g r a t e s a d j u s t a b l e l o a d l i n e v o l t a g e p o s i t i o n - i n g ( d r o o p ) a n d a d o p t s l o w s i d e r d s _ o n f o r c h a n n e l - c u r - r e n t b a l a n c e . t h e a u t o m a t i c p h a s e r e d u c t i o n a n d o v e r - c u r r e n t p r o t e c - t i o n a r e a c c o m p l i s h e d t h r o u g h c o n t i n u o u s i n d u c t o r d c r s c u r r e n t s e n s i n g . t h e a p w 8 7 0 0 a l s o i m p l e m e n t a o n e - b i t v i d c o n t r o l o p - e r a t i o n i n w h i c h t h e f e e d b a c k v o l t a g e i s r e g u l a t e d a n d t r a c k s e x t e r n a l i n p u t r e f e r e n c e v o l t a g e . t h i s c o n t r o l l e r p r o t e c t i o n f e a t u r e s i n c l u d e o v e r - t e m p e r a t u r e ( o t p ) , o v e r - v o l t a g e ( o v p ) , u n d e r - v o l t a g e ( u v p ) a n d o v e r - c u r r e n t p r o t e c t i o n s ( o c p ) . t h e d e v i c e a l s o p r o v i d e s a p o w e r - o n - r e s e t f u n c t i o n a n d a p r o g r a m m a b l e s o f t - s t a r t t o p r e v e n t w r o n g o p e r a t i o n a n d l i m i t t h e i n p u t s u r g e c u r r e n t d u r i n g p o w e r - o n o r s t a r t - u p . t h e a p w 8 7 0 0 i s a v a i l a b l e i n q f n 4 x 4 - 2 4 p a c k a g e s . s i m p l i f i e d a p p l i c a t i o n c i r c u i t fb refin rt/en comp psi ss v in v out ugate1 ugate2 lgate2 lgate1 vref on off
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n p i n c o n f i g u r a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v vcc input supply voltage ( v v cc to gnd) - 0.3 ~ 16 v v pvcc gate driver supply voltage (v pvcc to gnd) - 0.3 ~ v vcc +1 v boot1/2 to phase1/2 voltage - 0.3 ~ 16 v boot1/2 to gnd voltage - 0.3 ~ 30 v > 200ns - 0.3 ~ v boot1/2 +0.3 v ugate1/2 to phase1/2 voltage < 200ns - 5 ~ v boot1/2 +5 v > 200ns - 0.3 ~ v vcc +0.3 v v lgate1/2 lgate1/2 to gnd voltage < 200ns - 5 ~ v vcc +5 v > 200ns - 0.3 ~ 16 v v phase1/2 phase1/2 to gnd voltage < 200ns - 10 ~ 30 v refin, vref, rt/en, iofs, comp, fb, eap, ss, csp, csn, psi, vid, rset to agnd voltage - 0.3 ~ 7 v agnd to gnd - 0.3 +0.3 v p d power dissipation 2.5 w apw 8700 handling code tem perature range package code package code qa : qfn4x4-24 operating ambient temperature range i : -40 to 85 o c handling code tr : tape & reel assembly material g : halogen and lead free device apw 8700 qa : assembly material xxxxx - date code APW8700 xxxxx refin vref rt/en iofs comp a g n d e a p c s p vcc pvcc lgate1 phase1 ugate1 fb boot1 (exposed pad) gnd 17 16 15 14 13 18 2 3 4 5 6 1 23 22 21 20 19 24 8 9 10 11 12 7 qfn4x4-24 top view s s c s n p s i l g a t e 2 p h a s e 2 r s e t v i d b o o t 2 u g a t e 2 APW8700
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 3 a b s o l u t e m a x i m u m r a t i n g s ( c o n t . ) ( n o t e 1 ) symbol parameter rating unit t j maximum junction temperature 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum lead soldering temperature (10 seconds ) 26 0 o c t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja junction - to - ambient resistance in free air (note 2) qfn4x4 - 24 41 o c/w q jc junction - to - case resistance qfn4x4 - 24 9 o c/w note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. symbol parameter range unit v vcc vcc supply voltage ( v v cc to gnd) 4.5 ~ 13.2 v v out v out to gnd 0.6 ~ 5.5 v v in converter input voltage 2 ~ 13.2 v f osc oscillator frequency 100 ~ 800 khz i out converter output current 0 ~ 60 a t a ambient temperature - 40 ~ 85 o c t j junction temperature - 4 0 ~ 125 o c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 ) n o t e 3 : r e f e r t o t h e a p p l i c a t i o n c i r c u i t f o r f u r t h e r i n f o r m a t i o n . e l e c t r i c a l c h a r a c t e r i s t i c s apw 8700 symbol parameter test condition s min. typ. max. unit supply current vcc supply voltage range 4.5 - 13.2 v i dd_sd no switching, rt/en=gnd - 4 5 ma i dd input dc bias current ugate1/2, lgate1/2 open, switching - 5 7 ma v pvcc regulated supply voltage rt/en=gnd, i pvcc =0ma 8 9 10 v por threshold of vcc 3.8 4.1 4.4 v por hysteresis 0.3 0.5 0.6 v por threshold of pvcc 3.8 4.1 4.4 v por hysteresis 0.3 0.5 0.6 v refer to figure 1 in the ?typical application circuits?. these specifications apply over v vcc = 12v, ta= 25 o c, unless otherwise noted.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) apw 8700 symbol parameter test condition s min. typ. max. unit chip enable/frequency setting i rt/en rt/en source current rt/en=gnd - - 120 m a rt/en shutdown threshold 0.45 0.5 0.55 v enable debounce time rt/en high debounce - 200 - m s v rt/e n rt/en voltage r rt/en b =33k w - 1 - v switching frequency setting range 100 - 800 khz f osc free run switching frequency r rt/en =33k w 255 300 345 khz g f osc switching frequency accuracy f osc =200khz~500khz - 15 - 15 % soft - start i ss soft - start current dur ing soft - start - 20 - m a ss source/sink current capability after soft - start - 200 - m a oscillator maximum duty cycle - 85 - % minmum duty cycle - 0 - % g v osc ramp amplitude v vcc =12v - 1.5 - v power saving mode v psi threshold voltage to enter du al phase v psi rising 0.55 0.6 0.65 v g v psi hysteresis to enter single phase v psi falling - 0.2 - v 2 phase to single phase debounce continuously - 0.2 - ms reference voltage v ref reference voltage accuracy i ref =100 a, t j = - 20 o c ~ 70 o c 1.98 2.00 2.02 v vref maximum output current vref=gnd 20 - - ma g v ref reference voltage load regulation i ref =0~2ma - 5 - 5 mv v refin - v fb , v refin =0.8v~2v, r drp =0 w - 5 - 5 mv v fb output voltage accuracy v fb operating range 0.2 - v ref v error amplifier open - loop dc g ain (note 4) r l = 10k w , c l =10pf - 80 - v/v open - loop bandwidth (note 4) r l = 10k w , c l =10pf - 20 - mhz slew rate (note 4) r l = 10k w , c l =10pf - 8 - v/ m s fb input leakage current v fb =1v - 0.1 0.5 m a comp high voltage r l = 10k w , c l =10pf - 4.8 - v/ m s v comp comp low voltage r l = 10k w , c l =10pf - 0.2 - m a maximum comp source current v comp =2v - 2 - ma i comp maximum comp sink current v comp =2v - 2 - ma refer to figure 1 in the ?typical application circuits?. these specifications apply over v vcc = 12v, ta= 25 o c, unless otherwise noted.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 5 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) apw 8700 symbol parameter test condition s min. typ. max. unit total current sense i csn_max maximum sourcing current 100 - - m a gm amplifier offset - 5 - 5 mv i csn_ocp over - current protection threshold level 55 60 65 m a droop accuracy i drp /i csn 90 100 110 % psi accuracy i psi /i csn 90 100 110 % phase current sense gm trans - conductance - 1.0 - ma/v 100k w from iofs to vref 1.425 1.5 1.575 v v iofs iofs voltage 100k w from iofs to gnd 0.475 0.5 0.525 v vid control input v ih logic high t hreshold level 1.2 - - v v il logic low threshold level - - 0.4 v r rset on resistance of rset mosfet vid=high - 20 - w i rset leakage current of rset pin v rset =2v, vid=gnd - - 0.1 m a gate driver r ug_src upper side gate sourcing i ugate =100ma sourcing - 2 4 w r ug_snk upper side gate sinking i ugate =100ma sinking - 1.5 3 w r lg_src low side gate sourcing i lgate =100ma sourcing - 2 4 w r lg_snk low side gate sinking i lgate =100ma sinking - 1 2 w t dt dead - time - 30 - ns protection over voltage protection (ovp) v fb /v eap 125 130 135 % over voltage hysteresis - 20 - % under voltage protection (uvp) v fb /v eap 45 50 55 % over current protection (ocp) i csn 55 60 65 m a over temperature protection (otp) - 150 - o c over temperature hysteresis - 20 - o c refer to figure 1 in the ?typical application circuits?. these specifications apply over v vcc = 12v, ta= 25 o c, unless otherwise noted. note 4: guarantee by design, not production test
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 6 p i n d e s c r i p t i o n pin name function 1 refin external reference input. this is input pin of external reference voltage. connect a voltage divider from vref to refin to agnd to set the reference voltage. 2 vref reference voltage output. this is the output pin of high precis ion 2v reference voltage. bypass this pin with a 1 m f ceramic capacitor to agnd . 3 rt/en operation frequency setting. connecting a resistor between this pin and a gnd to set the operation frequency. pull this pin to ground to shut down the APW8700 . 4 iofs current balance adjustment. connect a resistor fro m this pin to vref or gnd to adjust the current sharing. 5 comp error amplifier output. use this pin in combination with the fb pin to compensate the voltage - control feedback loop of the converter. 6 fb feedback voltage. this pin is the inverting input t o the error amplifier. use this pin in combination with the comp pin to compensate the voltage control feedback loop of the converter. 7 agnd analog ground . connect this pin to the gnd pin where the output voltage is to be regulated. 8 eap non - inverting input of error amplifier. connect a resistor to ss pin to set the droop slope. 9 ss soft start output. connect a capacitor to gnd to set the soft start interval. 10 csn inverting input of current sensing amplifier. 11 csp non - inverting input of current sensing amplifier. 12 psi power saving indicator . connect a resistor from psi to a gnd to set the power saving mode threshold current level. connect this pin to vref for always two phase s operation. short this pin to ground for always single - phase operatio n. don ? t left this pin floating. 13 boot1 bootstrap supply for the floating high - side gate driver of channel 1 . connect the bootstrap capacitor between the boot 1 pin and the phase 1 pin to form a bootstrap circuit. the bootstrap capacitor provides the char ge to turn on the high - side mos fet. typical values for cboot range from 0.1f to 1f. ensure that cboot is placed near the ic. 14 ugate1 upper gate driver output for channel 1. connect this pin to the gate of high - side mosfet. this pin is monitored by the adaptive shoot - through protecti on circuitry to determine when the high - side mosfet has turned off. 15 phase1 switch node for channel 1. connect this pin to the source of high - side mosfet and the drain of the low - side mosfet. this pin is used as sink for ugate 1 driver. this pin is also monitored by the adaptive shoot - through protection circuitry to determine when the high - side mosfet has turned off. 16 lgate1 low - side gate driver output for channel 1. connect this pin to the gate of low - side mosfet. this pin is monitored by the adaptive shoot - through protection circuitry to determine when the low - side mosfet has turned off. 17 pvcc supply voltage for gate driver. this pin is the output of internal 9v ldo. it provides current for gate drives. bypass this pin with a minimum 1 m f ceramic ca pacitor. if vcc below 7v, connect this pin to vcc is recommended. 18 vcc supply voltage. this pin provides current for internal control circuit and 9v ldo. bypass this pin with a minimum 1 m f ceramic capacitor next to the ic. 19 lgate2 low - side gate drive r output for channel 2 . connect this pin to the gate of low - side mosfet. this pin is monitored by the adaptive shoot - through protection circuitry to determine when the low - side mosfet has turned off. 20 phase2 switch node for channel 2 . connect this pin t o the source of high - side mosfet and the drain of the low - side mosfet. this pin is used as sink for ugate2 driver. this pin is also monitored by the adaptive shoot - through protection circuitry to determine when the high - side mosfet has turned off. 21 ugat e2 upper gate driver output for channel 2 . connect this pin to the gate of high - side mosfet. this pin is monitored by the adaptive shoot - through protection circuitry to determine when the high - side mosfet has turned off.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 7 p i n d e s c r i p t i o n ( c o n t . ) pin name function 22 boot2 bootstrap supply for the floating high - side gate driver of channel 2 . connect the bootstrap capacitor between the boot 2 pin and the phase 2 pin to form a bootstrap circuit. the bootstrap capacitor provides the charge to turn on t he high - side mosfet. typical value s for cboot range from 0.1f to 1f. ensure that cboot is placed near the ic. 23 vid vid input. this pin is used to adjust reference voltage. logic high turns on the internal mosfet connected to rset pin. 24 rset reference voltage setting. this pin is an open drain output that is pulled low when vid = high. connect a resistor from this pin to refin pin to set the reference voltage. exposed pad gnd power ground. tie this p ad to the ground island/plane through the lowest impedance connection available.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 8 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s r e f e r e n c e v o l t a g e v s . j u n c t i o n t e m p e r a t u r e u g a t e d r i v e r o n r e s i s t a n c e v s . p v c c v o l t a g e l g a t e d r i v e r o n r e s i s t a n c e v s . s u p p l y v o l t a g e p v c c v o l t a g e v s . s u p p l y v o l t a g e r e f e r t o t h e ? t y p i c a l a p p l i c a t i o n c i r c u i t s ? , v i n = 1 2 v , v o u t = 1 . 0 5 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d r e f e r e n c e v o l t a g e v s . s u p p l y v o l t a g e junction temperature , t j ( o c ) 1 . 980 1 . 985 1 . 990 1 . 995 2 . 000 2 . 005 2 . 010 2 . 015 2 . 020 - 40 - 20 0 20 40 60 80 100 120 140 160 r e f e r e n c e v o l t a g e , v r e f ( v ) 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 4 5 6 7 8 9 pvcc voltage , v pvcc ( v ) u g a t e d r i v e r o n r e s i s t a n c e ( w ) ugate source ugate sink l g a t e d r i v e r o n r e s i s t a n c e ( w ) supply voltage , v vcc ( v ) 4 5 6 7 8 9 10 11 12 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 lgate sink lgate source p v c c v o l t a g e , v p v c c ( v ) supply voltage , v vcc ( v ) 4 5 6 7 8 9 10 11 12 13 14 0 1 2 3 4 5 6 7 8 9 10 i pvcc = 10 ma 4 5 6 7 8 9 10 11 12 13 14 1 . 95 1 . 96 1 . 97 1 . 98 1 . 99 2 2 . 01 2 . 02 2 . 03 2 . 04 2 . 05 r e f e r e n c e v o l t a g e , v r e f ( v ) supply voltage , v vcc ( v )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 9 o p e r a t i n g w a v e f o r m s e n a b l e s h u t d o w n p o w e r o n p o w e r o f f time: 500 m s/div time: 500 m s/div time: 500 m s/div time: 50 m s/div 1 4 3 2 v rt , 1 v / div , dc v phase 1 , 5 v / div , dc v ss , 0 . 5 v / div , dc v out , 0 . 5 v / div , dc 1 4 3 2 v rt , 1 v / div , dc v phase 1 , 10 v / div , dc v ss , 0 . 5 v / div , dc v out , 0 . 5 v / div , dc 1 4 3 2 v rt , 1 v / div , dc v phase 1 , 5 v / div , dc v ss , 0 . 5 v / div , dc v out , 0 . 5 v / div , dc 1 4 3 2 v rt , 1 v / div , dc v phase 1 , 10 v / div , dc v ss , 0 . 5 v / div , dc v out , 0 . 5 v / div , dc
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 1 0 o p e r a t i n g w a v e f o r m s p s i o v p o c p time: 50 m s/div time: 10 m s/div time: 20 m s/div 1 3 2 v psi , 1 v / div , dc v phase 1 , 10 v / div , dc v phase 2 , 10 v / div , dc 1 3 2 v fb , 1 v / div , dc v ugate 1 , 10 v / div , dc v lgate 1 , 10 v / div , dc 1 4 3 2 v ss , 1 v / div , dc v out , 1 v / div , dc i l 1 , 10 a / div , dc i l 2 , 10 a / div , dc i l 1 + i l 2 , 20 a / div , dc 3 + 4
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 1 1 b l o c k d i a g r a m eap pvcc phase1 boot1 ugate1 lgate1 vcc pvcc phase2 boot2 ugate2 lgate2 vcc logic control fb v osc1 v osc2 comp ss refin logic control psi csn csp rset vref vid internal regulator 1 vcc pvcc power saving setting power on reset gnd rt/en 1v 0.5v enable internal regulator 2 error amplifier current limit buffer iofs over current protection gm amplifier current balance agnd i drp oscillator
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 1 2 t y p i c a l a p p l i c a t i o n c i r c u i t fb refin rt / en comp psi ss v in = 12 v v out ugate 1 ugate 2 lgate 2 lgate 1 vref csp agnd csn phase 1 phase 2 boot 1 boot 2 ( option ) phase 2 phase 1 eap rset vid vcc gnd iofs on off 1 k 1 f ( option ) 0 . 8 h 1 k 8 . 1 k 47 nf 0 40 k 33 k 680 0 . 27 k 220 nf 10 nf 100 nf 12 r apm 3106 apm 3109 apm 3106 apm 3109 0 . 1 f 0 . 1 f 0 . 1 f nc 3 k 1 f 0 . 8 h 820 fx 3 10 fx 2 10 fx 2 10 fx 2 270 fx 2 10 k 2 n 7002 pvcc 1 f v out vref ( option )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 1 3 f u n c t i o n d e s c r i p t i o n v c c p o w e r - o n - r e s e t ( p o r ) t h e p o w e r - o n - r e s e t ( p o r ) c i r c u i t c o m p a r e s t h e i n p u t v o l t a g e a t v c c w i t h t h e p o r t h r e s h o l d ( 4 . 1 v r i s i n g , t y p i c a l ) t o e n s u r e t h e i n p u t v o l t a g e i s h i g h e n o u g h f o r r e l i a b l e o p e r a t i o n . t h e 0 . 5 v ( t y p ) h y s t e r e s i s p r e v e n t s s u p p l y t r a n - s i e n t s f r o m c a u s i n g a r e s t a r t . o n c e t h e i n p u t v o l t a g e e x - c e e d s t h e p o r r i s i n g t h r e s h o l d , s t a r t u p b e g i n s . w h e n t h e i n p u t v o l t a g e f a l l s b e l o w t h e p o r f a l l i n g t h r e s h o l d , t h e c o n t r o l l e r t u r n s o f f t h e c o n v e r t e r . v r e f this is the output pin of high precision 2v reference voltage. bypass this pin with a 1 m f ceramic capacitor to agnd. the vref have capability to drive 20ma output current. f i g u r e 1 . p o w e r o n / o f f s e q u e n c e s o f t - s t a r t after the vcc voltage exceeds the por voltage threshold and the rt/en voltage exceeds 0.5v, the device initials a start-up process and then ramps up the output voltage to the setting of output voltage. a 20 m a current source starts to charge the capacitor (c ss ) connected with ss and agnd pins. connect error amplifier non-inverting input, eap, to ss. the v fb starts to rise with the same rate as the soft-start voltage. once the ss voltage reaches 80% of vrefin, the soft-start process is completed after 3ms. after the soft-start process is completed, the ss could source/sink 200 m a. figure 2 shows the simplified voltage control loop of APW8700. vref is a reference voltage output with 1% accuracy and up to 20ma sourcing capability. rset is an open drain output that is controlled by vid pin. rset is pulled to fbrtn when vid = 1 and is set high imped- ance when vid = 0. ss ss ss ss c a 20 c i dt dv = = ss ss ss ss c a 200 c i dt dv = = d u r i n g s o f t - s t a r t a f t e r s o f t - s t a r t 2 r 1 r 2 r v v ref ss + = ) 3 r // 2 r ( 1 r 3 r // 2 r v v ref ss + = v i d = 0 v i d = 1 vid rset refin vref agnd comp fb eap ss v out i drp error amplifier current limit buffer r1 r3 r2 r drp c ss f i g u r e 2 . s i m p l i f i e d v o l t a g e c o n t r o l l o o p vcc pvcc ref ss = eap por rt / en vid uvlo
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 1 4 f u n c t i o n d e s c r i p t i o n ( c o n t . ) r t / e n i s a m u l t i f u n c t i o n p i n . p u l l r t / e n b e l o w 0 . 5 v t o s h u t s d o w n t h e d e v i c e . c o n n e c t i n g a r e s i s t o r b e t w e e n t h i s p i n a n d g n d t o s e t t h e o p e r a t i o n f r e q u e n c y . t h e o p - e r a t i o n f r e q u e n c y r a n g e c o u l d b e s e t f r o m 1 0 0 k h z t o 8 0 0 k h z . i n s h u t d o w n m o d e , t h e u g a t e x a n d l g a t e x a r e p u l l e d t o p h a s e x a n d g n d r e s p e c t i v e l y . w h e n t h e p u l l - d o w n d e v i c e i s r e l e a s e d , t h e a p w 8 7 0 0 i n i t i a t e a s o f t - s t a r t p r o c e s s . s h u t d o w n c o n t r o l a n d f r e q u e n c y s e t t i n g the differential current of the current balance control cir- cuit (i sen1 -i sen2 ) is used to fine-tune the comp1/2 voltage. the v comp1 and v comp2 will increase or decrease because of these two currents. for example, when i sen1 >i sen2 , the v comp1 will decrease and the v comp2 will increase. therefore, the duty of pwm1 will decrease and the duty of pwm2 will increase. then, the device will reduce i l1 current and in- crease i l2 current for current sharing, vice verse. c u r r e n t b a l a n c e r the APW8700 adopts parasitic on-resistance of the lower switches current balance as show in figure 4. when the lower switches turn on, the gm amplifier senses the volt- age drop across the lower switches and converts it into current signal each time it turns on. the sampled and held current is expressed as: the switching frequency, f osc , could be calculated as: ) khz ( ) k ( r 10000 f rt osc w = 100 1000 10 100 r rt (k w) s w i t c h i n g f r e q u e n c y ( k h z ) f i g u r e 3 . s w i t c h i n g f r e q u e n c y v s . r t r e s i s t a n c e x offset x ) on ( ds x senx r v r r il i + = below shows the circuit of sensing inductor current. con- necting a series resistor (r s ) and a capacitor (c s ) net- work in parallel with the inductor and measuring the volt- age (v c ) across the capacitor can sense the inductor current. phase1 v offset sample & hold v offset i sen1 i sen2 phase2 i ofs iofs i sen1 - i sen 2 i ofs current balance comp comp1 comp2 rx rx f i g u r e 4 . c u r r e n t b a l a n c e s c h e m e c u r r e n t s e n s e l1 phase1 v out r s dcr1 c s r csn csn csp i csn + v c - eap psi i drp i psi f i g u r e 5 . d c r c u r r e n t s e n s e s c h e m e
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 1 5 f u n c t i o n d e s c r i p t i o n ( c o n t . ) o v e r c u r r e n t p r o t e c t i o n ( o c p ) the APW8700 feature an over current protection adopt current sensing. when i csn exceed 60 m a at operation, the over current occurs. in over-current protection, the ic shuts off the converter. the i csn can be describe as: the equations of the sensing network are: ) 1 dcr 1 sl ( ) s ( i ) s ( v 1 l 1 l + = in some high current applications, a requirement on pre- cisely controlled output impedance is imposed. this de- pendence of output voltage on load current is often termed droop regulation. as shown in figure 4, the droop control block generates a voltage through external resistor r drp and then set the droop voltage. the droop voltage, v drp , is proportional to the total current in two channels. as shown in the following equation: d r o o p s e t t i n g s s 1 l s s 1 l c c sr 1 ) 1 dcr 1 sl ( ) s ( i c sr 1 1 ) s ( v ) s ( v + + = + = take 1 dcr 1 l c r s s = if the above is true, the voltage across the capacitor c s equal to voltage drop across the inductor dcr1, and the voltage v c is proportional to the inductor current i l1 . 1 l c i 1 dcr v = csn 1 l csn c csn r 1 dcr i r v i = = where i l1 is the inductor current of phase 1 dcr1 is the inductor resistance of phase 1 due to the APW8700 implement current balance circuit. at two phase operation, the i l1 equal half of output current, i out . csn out csn r 2 1 dcr i i = csn out csn c csn r 2 1 dcr i r v i = = the APW8700 initial a soft-start process until recycle por or en/rt. the APW8700 implements automatic phase reduction that turns off phase 2 at light load condition and reduces both switching and conduction losses. the automatic phase reduction maintains high power conversion effi- ciency over the output current range. the output current is sensed and mirrored to psi pin as: a u t o m a t i c p h a s e r e d u c t i o n csn out csn psi r 2 1 dcr i i i = = the i psi creates a voltage v psi as: csn psi out psi psi psi r 2 r 1 dcr i i r v = = the APW8700 operates at dual phase if v psi exceeds 0.6v and at single phase at v psi below 0.4v. there is a 200mv hystersis at the phase change threshold. there is a 0.2ms delay when entering single phase operation and no time delay when entering dual phase operation. when operating single phase, both ugate2 and lgate2 are turned off. drp drp ss fb r i v v - = where i drp is the droop current that mirrored from i csn . the output voltage also can be describe as: csn drp out ss drp drp ss fb r 2 r 1 dcr i v r i v v - = - =
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 1 6 f u n c t i o n d e s c r i p t i o n ( c o n t . ) t h e a p w 8 7 0 0 i n t e g r a t e d i o f s a l l o w s t h e o f f s e t c u r r e n t t o a d j u s t p h a s e c u r r e n t . t h e i o f s p i n v o l t a g e i s n o m i n a l 0 . 5 v w h e n c o n n e c t i n g a r e s i s t o r t o g n d a n d 1 . 5 v w h e n c o n n e c t i n g a r e s i s t o r t o v r e f . c o n n e c t i n g a r e s i s t o r f r o m i o f s p i n t o g n d g e n e r a t e a c u r r e n t s o u r c e a s : i ofs = 0 . 5 v / r iofs t h i s c u r r e n t i s a d d t o p h a s e 1 c u r r e n t s i g n a l i s e n 1 f o r c u r - r e n t b a l a n c e . c o n s e q u e n t l y , p h a s e 2 w i l l s h a r e m o r e p e r c e n t a g e o f o u t p u t c u r r e n t . c o n n e c t i n g a r e s i s t o r f r o m i o f s p i n t o v r e f g e n e r a t e s a c u r r e n t s o u r c e a s : i ofs = ( 2 v - 1 . 5 v ) / r iofs t h i s c u r r e n t i s a d d t o p h a s e 2 c u r r e n t s i g n a l i sen2 f o r c u r - r e n t b a l a n c e . c o n s e q u e n t l y , p h a s e 1 w i l l s h a r e m o r e p e r c e n t a g e o f o u t p u t c u r r e n t . o f f s e t c u r r e n t a d j u s t t h e o v e r - t e m p e r a t u r e c i r c u i t l i m i t s t h e j u n c t i o n t e m p e r a - t u r e o f t h e a p w 8 7 0 0 . w h e n t h e j u n c t i o n t e m p e r a t u r e e x - c e e d s 1 5 0 o c , a t h e r m a l s e n s o r p u l l s u g t a e x a n d l g a t e x l o w , a l l o w i n g t h e d e v i c e s t o c o o l . t h e t h e r m a l s e n s o r a l l o w s t h e c o n v e r t e r s t o s t a r t a s o f t - s t a r t p r o c e s s a n d r e g u l a t e s t h e o u t p u t v o l t a g e a g a i n a f t e r t h e j u n c t i o n t e m - p e r a t u r e c o o l s b y 2 0 o c . t h e o t p i s d e s i g n e d w i t h a 2 0 o c h y s t e r e s i s t o l o w e r t h e a v e r a g e j u n c t i o n t e m p e r a t u r e ( t j ) d u r i n g c o n t i n u o u s t h e r m a l o v e r l o a d c o n d i t i o n s i n - c r e a s i n g t h e l i f e t i m e o f t h e d e v i c e . o v e r - t e m p e r a t u r e p r o t e c t i o n ( o t p ) t h e o v e r - v o l t a g e p r o t e c t i o n ( o v p ) c i r c u i t m o n i t o r s t h e f b ( v fb ) v o l t a g e t o p r e v e n t t h e o u t p u t f r o m o v e r - v o l t a g e . w h e n t h e v fb r i s e s t o 1 3 0 % o f t h e e a p v o l t a g e ( v eap ) , t h e a p w 8 7 0 0 t u r n s o f f h i g h - s i d e a n d t u r n o n l o w - s i d e m o s f e t s t o s i n k o u t p u t v o l t a g e ( v out ) . a s s o o n a s t h e v fb f a l l s b e l o w 1 1 0 % o f v eap , t h e o v p c o m p a r a t o r i s d i s e n g a g e d . t h e c h i p w i l l r e s t o r e i t s n o r m a l o p e r a t i o n . o v p t h e u n d e r - v o l t a g e p r o t e c t i o n c i r c u i t m o n i t o r s t h e v o l t a g e o n f b ( v fb ) b y u n d e r - v o l t a g e ( u v ) c o m p a r a t o r t o p r o t e c t t h e p w m c o n v e r t e r a g a i n s t s h o r t - c i r c u i t c o n d i t i o n s . w h e n t h e v fb f a l l s b e l o w t h e f a l l i n g u v p t h r e s h o l d ( 5 0 % v eap ) , a f a u l t s i g n a l i s g e n e r a t e d a n d t h e d e v i c e t u r n s o f f h i g h - s i d e a n d l o w - s i d e m o s f e t s . t h e c o n v e r t e r s h u t s d o w n a n d t h e o u t p u t i s l a t c h e d t o b e f l o a t i n g . t h e a p w 8 7 0 0 w i l l i n i t i a l s a s o f t - s t a r t p r o c e s s u n t i l r e - c y c l e r t / e n o r v c c u v p
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 1 7 a p p l i c a t i o n i n f o r m a t i o n pwm compensation the output lc filter of a step down converter introduces a double pole, which contributes with -40db/decade gain slope and 180 degrees phase shift in the control loop. a compensation network among comp, fb, and v out should be added. the compensation network is shown in figure 9. the output lc filters consists of the output inductors and output capacitors. for two-phase convertor, when assuming v in1 =v in2 =v in , l1=l2=l, the transfer function of the lc filter is given by: the poles and zero of this transfer functions are: the f lc is the double-pole frequency of the two-phase lc filters, and f esr is the frequency of the zero introduced by the esr of the output capacitors. figure 6. the output lc filter figure 7. frequency resopnse of the lc filters f lc f esr -40db/dec -20db/dec frequency(hz) g a i n ( d b ) the pwm modulator is shown in figure 8. the input is the output of the error amplifier and the output is the phase node. the transfer function of the pwm modulator is given by : figure 8. the pwm modulator the compensation network is shown in figure 9. it pro- vides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. the transfer function of error amplifier is given by : ( ) ? ? ? ? + ? ? ? ? + + ? ? ? ? ? + + ? ? ? ? + + = c3 r3 1 s c2 c1 r2 c2 c1 s s c3 r3 r1 1 s c2 r2 1 s c1 r3 r1 r3 r1 out esr c esr 2 1 f p = ? ? ? ? + ? ? ? ? + = = sc3 1 r3 r1// sc2 1 r2 // sc1 1 v v gain out comp amp osc in pwm v v gain d = osc output of error amplifier d v osc pwm comparator driver driver phase v in 1 c esr s c l 2 1 s c esr s 1 gain out ut o 2 out lc + + + = out lc c l 2 1 2 1 f p = v phase1 l1=l v out c out esr v phase2 l2=l the pole and zero frequencies of the transfer function are: c2 r2 2 1 f z1 p = ( ) c3 r3 r1 2 1 f z2 + p = ? ? ? ? + p = c2 c1 c2 c1 r2 2 1 f p1 c3 r3 2 1 f p2 p =
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 1 8 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) pwm compensation (cont.) figure 9. compensation network the closed loop gain of the converter can be written as: gain lc x gain pwm x gain amp figure 10. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. using the below guidelines should give a compensation similar to the curve plotted. a stable closed loop has a -20db/ decade slope and a phase margin greater than 45 degree. 1. choose a value for r1, usually between 1k and 5k. 2. select the desired zero crossover frequency f o = (1/5 ~ 1/10) x f sw use the following equation to calculate r2: 3. place the first zero f z1 before the output lc filter double pole frequency f lc . f z1 = 0.75 x f lc calculate the c2 by the equation: r1 f f v v r2 lc o in osc d = 4. set the pole at the esr zero frequency f esr : f p1 = f esr calculate the c1 by the following equation: 0.75 f r2 2 1 c2 lc p = 1 f c2 r2 2 c2 c1 esr - p = 5. set the second pole f p2 at the half of the switching frequency and also set the second zero f z2 at the output lc filter double pole f lc . the compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at f p2 with the capabilities of the error amplifier. f p2 = 0.5 x f sw f z2 = f lc combine the two equations will get the following component calculations: f lc frequency(hz) g a i n ( d b ) 20log (r2/r1) 20log (v in / g v osc ) f z1 f z2 f p1 f p2 f esr pwm & filter gain converter gain compensation gain v ref v out v comp r 1 r 3 c 3 r 2 c 2 c 1 fb 1 f 2 f r1 r3 lc sw - = sw f r3 1 c3 p = figure 10. converter gain and frequency o u t p u t i n d u c t o r s e l e c t i o n t h e d u t y c y c l e ( d ) o f a b u c k c o n v e r t e r i s t h e f u n c t i o n o f t h e i n p u t v o l t a g e a n d o u t p u t v o l t a g e . o n c e a n o u t p u t v o l t - a g e i s f i x e d , i t c a n b e w r i t t e n a s :
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 1 9 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) o u t p u t i n d u c t o r s e l e c t i o n ( c o n t . ) in out v v d = w h e r e f s w i s t h e s w i t c h i n g f r e q u e n c y o f t h e r e g u l a t o r . a l t h o u g h t h e i n d u c t o r v a l u e a n d f r e q u e n c y a r e i n c r e a s e d a n d t h e r i p p l e c u r r e n t a n d v o l t a g e a r e r e d u c e d , a t r a d e o f f e x i s t s b e t w e e n t h e i n d u c t o r ? s r i p p l e c u r r e n t a n d t h e r e g u - l a t o r l o a d t r a n s i e n t r e s p o n s e t i m e . a s m a l l e r i n d u c t o r w i l l g i v e t h e r e g u l a t o r a f a s t e r l o a d t r a n - s i e n t r e s p o n s e a t t h e e x p e n s e o f h i g h e r r i p p l e c u r r e n t . i n c r e a s i n g t h e s w i t c h i n g f r e q u e n c y ( f s w ) a l s o r e d u c e s t h e r i p p l e c u r r e n t a n d v o l t a g e , b u t i t w i l l i n c r e a s e t h e s w i t c h i n g l o s s o f t h e m o s f e t s a n d t h e p o w e r d i s s i p a - t i o n o f t h e c o n v e r t e r . t h e m a x i m u m r i p p l e c u r r e n t o c - c u r s a t t h e m a x i m u m i n p u t v o l t a g e . a g o o d s t a r t i n g p o i n t i s t o c h o o s e t h e r i p p l e c u r r e n t t o b e a p p r o x i m a t e l y 3 0 % o f t h e m a x i m u m o u t p u t c u r r e n t . o n c e t h e i n d u c t a n c e v a l u e h a s b e e n c h o s e n , s e l e c t a n i n d u c t o r t h a t i s c a p a b l e o f c a r r y i n g t h e r e q u i r e d p e a k c u r r e n t w i t h o u t g o i n g i n t o s a t u r a t i o n . i n s o m e t y p e s o f i n d u c t o r s , e s p e c i a l l y c o r e t h a t i s m a d e o f f e r r i t e , t h e r i p p l e c u r r e n t w i l l i n c r e a s e a b r u p t l y w h e n i t s a t u r a t e s . t h i s r e s u l t s i n a l a r g e r o u t - p u t r i p p l e v o l t a g e . for two-phase converter, the inductor value (l) determines the sum of the two inductor ripple currents, d i p-p , and af- fects the load transient reponse. higher inductor value reduces the output capacitors? ripple current and induces lower output ripple voltage. the ripple current can be approxminated by: o u t p u t c a p a c i t o r s e l e c t i o n o u tput voltage ripple and the transient volt age de- viation are factors that have to be taken into con- sideration when selecting output capacitor s . higher c apacitor value and lower esr reduce the output ripple and the load transient drop. therefore , selecting high performance low esr capacitors is recommended for switching regulator applications. in addition to high fre- quency noise related to mosfet turn-on and turn-off, the output voltage ripple includes the capacitance voltage drop d v cout and esr voltage drop d v esr caused by the ac peak-to-peak sum of the inductor?s current. t h e r i p p l e v o l t a g e o f o u t p u t c a p a c i t o r s c a n b e r e p r e s e n t e d b y : these two components constitute a large portion of the total output voltage ripple. in some applications, multiple capacitors have to be paralleled to achieve the desired esr value. if the output of the converter has to support another load with high pulsating current, more capaci- tors are needed in order to reduce the equivalent esr and suppress the voltage ripple to a tolerable level. a small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors are also must be considered. to support a load transient that is faster than the switching frequency, more capacitors are needed for re duc ing the voltage excursion during load step change. for getting same load transient response, the output capacitance of two-phase converter only needs around half of output capacitance of single-phase converter. another aspect of the capacitor selection is that the total ac current going through the capaci tors has to be less than the rated rms current specified on the ca- pacitors in order to prevent the capacitor from over- heating. i n p u t c a p a c i t o r s e l e c t i o n u s e s m a l l c e r a m i c c a p a c i t o r s f o r h i g h f r e q u e n c y d e c o u p l i n g a n d b u l k c a p a c i t o r s t o s u p p l y t h e s u r g e c u r - r e n t n e e d e d e a c h t i m e h i g h - s i d e m o s f e t t u r n s o n . p l a c e t h e s m a l l c e r a m i c c a p a c i t o r s p h y s i c a l l y c l o s e t o t h e m o s f e t s a n d b e t w e e n t h e d r a i n o f h i g h - s i d e m o s f e t a n d t h e s o u r c e o f l o w - s i d e m o s f e t . t h e i m p o r t a n t p a r a m e t e r s f o r t h e b u l k i n p u t c a p a c i t o r a r e t h e v o l t a g e r a t i n g a n d t h e r m s c u r r e n t r a t i n g . f o r r e l i a b l e o p e r a t i o n , s e l e c t t h e b u l k c a p a c i t o r w i t h v o l t a g e a n d c u r - r e n t r a t i n g s a b o v e t h e m a x i m u m i n p u t v o l t a g e a n d l a r g - e s t r m s c u r r e n t r e q u i r e d b y t h e c i r c u i t . t h e c a p a c i t o r v o l t - a g e r a t i n g s h o u l d b e a t l e a s t 1 . 2 5 t i m e s g r e a t e r t h a n t h e m a x i m u m i n p u t v o l t a g e a n d a v o l t a g e r a t i n g o f 1 . 5 t i m e s i s a c o n s e r v a t i v e g u i d e l i n e . f o r t w o - p h a s e c o n v e r t e r , t h e in out sw out in p - p v v l f 2v - v i = d esr p p esr sw out p p cout r i v f c 8 i v - - d = d d = d
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 2 0 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) f o r a t h r o u g h h o l e d e s i g n , s e v e r a l e l e c t r o l y t i c c a p a c i t o r s m a y b e n e e d e d . f o r s u r f a c e m o u n t d e s i g n , s o l i d t a n - t a l u m c a p a c i t o r s c a n b e u s e d , b u t c a u t i o n m u s t b e e x e r - c i s e d w i t h r e g a r d t o t h e c a p a c i t o r s u r g e c u r r e n t r a t i n g . i n p u t c a p a c i t o r s e l e c t i o n ( c o n t . ) r m s c u r r e n t o f t h e b u l k i n p u t c a p a c i t o r i s r o u g h l y c a l c u - l a t e d a s t h e f o l l o w i n g e q u a t i o n : m o s f e t s e l e c t i o n the APW8700 requires two n-channel power mosfets on each phase. these should be selected based upon r ds(on) , gate supply requirements, and thermal manage- ment requirements. in high-current applications, the mosfet power dissipation, package selection, and heatsink are the domi- nant design factors. the power dissipation includes two loss components, conduction loss, and switching loss. the conduction losses are the largest component of power dissipation for both the high-side and the low- side mosfets. these losses are distributed between the two mosfets according to duty factor (see the equa- tions below). only the high-side mosfet has switching losses since the low-side mosfets body diode or an external schottky rectifier across the lower mosfet clamps the switching node before the synchronous rec- tifier turns on. these equations assume linear voltage- current transitions and do not adequately model power loss due the reverse-recovery of the low-side mosfet body diode. the gate-charge losses are dissipated by the APW8700 and don?t heat the mosfets. however, large gate-charge increases the switching interval, t sw which increases the high-side mosfet switching losses. ensure that all mosfets are within their maxi- mum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. for the high-side and low-side mosfets, the losses are approximately given by the following equations: p high-side = i out 2 (1+ tc)(r ds(on) )d + (0.5)( i out )(v in )( t sw )f s w p low-side = i out 2 (1+ tc)(r ds(on) )(1-d) where i out is the load current tc is the temperature dependency of r ds(on) f sw is the switching frequency t sw is the switching interval d is the duty cycle note that both mosfets have conduction losses while the high- side mosfet include s an additional transi - tion loss. t he switching interval , t sw , is the function of l a y o u t c o n s i d e r a t i o n i n a n y h i g h s w i t c h i n g f r e q u e n c y c o n v e r t e r , a c o r r e c t l a y o u t i s i m p o r t a n t t o e n s u r e p r o p e r o p e r a t i o n o f t h e r e g u l a t o r . w i t h p o w e r d e v i c e s s w i t c h i n g a t h i g h e r f r e q u e n c y , t h e r e s u l t i n g c u r r e n t t r a n s i e n t w i l l c a u s e v o l t a g e s p i k e a c r o s s t h e i n t e r c o n n e c t i n g i m p e d a n c e a n d p a r a s i t i c c i r c u i t e l e m e n t s . a s a n e x a m p l e , c o n s i d e r t h e t u r n - o f f t r a n s i t i o n o f t h e p w m m o s f e t . b e f o r e t u r n - o f f c o n d i t i o n , t h e m o s f e t i s c a r r y i n g t h e f u l l l o a d c u r r e n t . d u r i n g t u r n - o f f , c u r r e n t s t o p s f l o w i n g i n t h e m o s f e t a n d i s f r e e w h e e l i n g b y t h e l o w s i d e m o s f e t a n d p a r a s i t i c d i o d e . a n y p a r a s i t i c i n d u c t a n c e o f t h e c i r c u i t g e n e r a t e s a l a r g e v o l t a g e s p i k e d u r i n g t h e s w i t c h i n g i n t e r v a l . i n g e n e r a l , u s i n g s h o r t a n d w i d e p r i n t e d c i r c u i t t r a c e s s h o u l d m i n i m i z e i n t e r c o n n e c t - i n g i m p e d a n c e s a n d t h e m a g n i t u d e o f v o l t a g e s p i k e . b e s i d e s , s i g n a l a n d p o w e r g r o u n d s a r e t o b e k e p t s e p a - r a t i n g a n d f i n a l l y c o m b i n e d u s i n g g r o u n d p l a n e c o n s t r u c - t i o n o r s i n g le point grounding. the best tie-point between the signal ground and the power ground is at the nega- tive side of the output capacitor on each channel, where there is less noise. noisy traces beneath the ic are not recommended. figure 11. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. components along the bold lines should be placed lose together. below is a checklist for your layout: the reverse transfer capacitance c rss . the (1+tc) term is a factor in the temperature dependency of the r ds(on) and can be extracted from the ?r ds(on) vs. temperature? curve of the power mosfet. 2d) - (1 2d 2 i i out rms =
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 2 1 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) l a y o u t c o n s i d e r a t i o n ( c o n t . ) t h e s i g n a l s g o i n g t h r o u g h t h e s e s t r a c e s h a v e b o t h h i g h d v / d t a n d h i g h d i / d t w i t h h i g h p e a k c h a r g i n g a n d d i s c h a r g i n g c u r r e n t . t h e t r a c e s f r o m t h e g a t e d r i v e r s t o t h e m o s f e t s ( u g a t e x a n d l g a t e x ) s h o u l d b e s h o r t a n d w i d e . p l a c e t h e s o u r c e o f t h e h i g h - s i d e m o s f e t a n d t h e d r a i n o f t h e l o w - s i d e m o s f e t a s c l o s e a s p o s s i b l e . m i n i m i z i n g t h e i m p e d a n c e w i t h w i d e l a y o u t p l a n e b e - t w e e n t h e t w o p a d s r e d u c e s t h e v o l t a g e b o u n c e o f t h e n o d e . i n a d d i t i o n , t h e l a r g e l a y o u t p l a n e b e t w e e n t h e d r a i n o f t h e m o s f e t s ( v i n a n d p h a s e x n o d e s ) c a n g e t b e t t e r h e a t s i n k i n g . for experiment result of accurate current sensing, the current sensing components are suggested to place close to the inductor part. to avoid the noise interference, the current sensing trace should be away from the noisy switching nodes. d e c o u p l i n g c a p a c i t o r s , t h e r e s i s t o r - d i v i d e r , a n d b o o t c a p a c i t o r s h o u l d b e c l o s e t o t h e i r p i n s . ( f o r e x a m p l e , p l a c e t h e d e c o u p l i n g c e r a m i c c a p a c i t o r c l o s e t o t h e d r a i n o f t h e h i g h - s i d e m o s f e t a s c l o s e a s p o s s i b l e ) . t h e i n p u t b u l k c a p a c i t o r s s h o u l d b e c l o s e t o t h e d r a i n o f t h e h i g h - s i d e m o s f e t , a n d t h e o u t p u t b u l k c a p a c i - t o r s s h o u l d b e c l o s e t o t h e l o a d s . t h e i n p u t c a p a c i - t o r ? s g r o u n d s h o u l d b e c l o s e t o t h e g r o u n d s o f t h e o u t p u t c a p a c i t o r s a n d l o w - s i d e m o s f e t . l o c a t e t h e r e s i s t o r - d i v i d e r c l o s e t o t h e f b p i n t o m i n i - m i z e t h e h i g h i m p e d a n c e t r a c e . i n a d d i t i o n , f b p i n t r a c e s c a n ? t b e c l o s e t o t h e s w i t c h i n g s i g n a l t r a c e s ( u g a t e x , l g a t e x , b o o t x , a n d p h a s e x ) . k e e p t h e switching nodes (ugatex, lgatex, bootx, and phasex) awa y f r o m s e n s i t i v e s m a l l s i g n a l n o d e s s i n c e t h e s e n o d e s a r e f a s t m o v i n g s i g n a l s . t h e r e f o r e , k e e p t r a c e s t o t h e s e n o d e s a s s h o r t a s p o s s i b l e a n d t h e r e s h o u l d b e n o o t h e r w e a k s i g n a l t r a c e s i n p a r a l - l e l w i t h t h e s e s t r a c e s o n a n y l a y e r . figure 11. layout guidelines boot 1 phase 1 ugate 1 lgate 1 v in 1 = v i n apw 8700 v in 2 = v in boot 2 phase 2 ugate 2 lgate 2 v out l o a d c s csn csp l 1 l 2 r s 1 r s 2 r csn
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 2 2 q f n 4 x 4 - 2 4 a d e a1 a3 pin 1 corner e 2 l d2 b e s y m b o l min. max. 1.00 0.00 0.18 0.30 2.50 2.80 0.05 2.50 a a1 b d d2 e e2 e l millimeters a3 0.20 ref qfn4x4-24 0.35 0.45 2.80 0.008 ref min. max. inches 0.039 0.000 0.008 0.012 0.098 0.110 0.098 0.014 0.018 0.80 0.110 0.031 0.002 4.00 bsc 0.157 bsc 4.00 bsc 0.157 bsc 0.50 bsc 0.020 bsc p a c k a g e i n f o r m a t i o n
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 2 3 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 qfn4x4 - 24 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0.40 4.30 ? 0.20 4.30 ? 0.20 1.30 ? 0.20 (mm) c a r r i e r t a p e & r e e l d i m e n s i o n s d e v i c e s p e r u n i t package type unit quantity q fn 4x4 - 24 tape & reel 3000 h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 2 4 t a p i n g d i r e c t i o n i n f o r m a t i o n q f n 4 x 4 - 2 4 user direction of feed c l a s s i f i c a t i o n p r o f i l e
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 2 5 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ tj=125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - j u n . , 2 0 1 1 a p w 8 7 0 0 w w w . a n p e c . c o m . t w 2 6 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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